1. Field of the Invention
This invention relates to integrated circuit device fabrication, and more particularly, to a fixture for electroplating metal bumps on the metallized circuit patterns on a semiconductor wafer.
2. Description of the Related Art
Metal bump contacts may be used in flip chip technology electrically to connect an integrated circuit to a substrate, and may be used in TAB (tape automated bonding) technology electrically to connect an integrated circuit to a leadframe. Typically, the bumps are electroplated onto metallized integrated circuit contacts on the surface of a semiconductor wafer at locations determined by a photoresist pattern on the wafer.
A common prior art technique for electroplating bump contacts on wafers was implemented by patterning the face of the wafer with photoresist, covering the backside of the wafer with photoresist or wax to prevent plating of the backside, then placing the wafer in a rack which holds the wafer vertically in a plating bath while carrying out the bump plating process.
U.S. Pat. No. 4,137,867 discloses a fixture for bump plating in which the backside of a wafer to be plated requires no coating to prevent plating of the backside. This fixture enables a cost savings to be realized by reducing the number of processing steps for bump plating. That is, the steps involved in coating the backside of a wafer are no longer necessary. This is made possible by a fixture which holds a wafer face down at the surface of the plating bath. Only the face of the wafer makes contact with the plating bath, while the backside is kept dry by directing a flow of nitrogen gas against the backside.
Both of the above prior art techniques result in a lowered yield due to air bubbles getting trapped in the bump vias (the cylindrically shaped cavities in the photoresist where bumps will be plated on the wafer) in the photoresist on the wafer face. The bubbles displace the plating solution in the vias and either prevent bumps from being plated where the bubbles are, or cause bumps to be plated which have inadequate shape or height. It is necessary to circulate the plating solution, or bath, during the plating process, and it is extremely difficult to circulate the bath without generating bubbles. When plating is performed on wafers having vertical or face down orientations in the plating bath, the possibility exists that air bubbles will be trapped in the vias. With these prior art wafer orientations, thickening the photoresist coating on the face of a wafer increases the likelihood that bubbles will be trapped in the vias.
When used with TAB or flip chip technology, it is desirable that the bumps be tall. Studies, including computer stress modeling, show that bumps give more stress relief, and thus greater reliability, than shorter bumps. The height of a wall formed bump is equal to the thickness of the photoresist on the face of the wafer. Since the depth of the vias is equal to the thickness of the photoresist, it is apparent that deep vias produce tall bumps. The deep vias are more prone to trapping bubbles than are the shallower vias when the vias are on wafers being bump plated by one of the prior art processes in which the wafers have either a vertical or face down orientation during plating. The aspect ratio of a bump (or via) is defined as height (depth) divided by width. Studies have shown that when the aspect ratio reaches approximately 0.4 or greater, many bubbles become trapped in the vias of wafers plated by the method disclosed in U.S. Pat. No. 4,137,867. When the aspect ratio is less than approximately 0.4, bubbles which rise in the fixture and touch the face of the wafer can be made to move along the face of the wafer to escape at the edge of the wafer by the circulation of the plating bath. Thus, the bubbles which reach the surface of the wafer do not become trapped in the vias. When the critical ratio of approximately 0.4 is reached, the flow of the bath is no longer able to sweep bubbles out of the vias, and plating may be prevented entirely in vias where there are bubbles, or the bumps may be misshapen.
Another important feature concerning bumps is their planarity. Planarity can be expressed in terms of the difference in height between the tallest and shortest bumps on a single integrated circuit chip or on an entire wafer. For example, if all bumps on a single chip were exactly the same height, their top surfaces would lie in a common plane and their planarity difference would be zero. If the tallest bump on a chip is 30 microns high and the shortest is 28 microns, then the planarity difference for the chip is 2 microns. When the planarity difference is low, planarity is said to be high.
Planarity is important because it influences the yield of good integrated circuits at assembly. Methods for making electrical contact with the bumps, using the TAB or flip chip processes, give maximum yields when planarity is high, and yield decreases as planarity decreases. When planarity is low, the likelihood increases that one of the bumps will not form a good electrical contact. This is especially true with flip chips since the substrate to be connected electrically to the bumps has a surface which is substantially planar. Loss of contact with a single bump on a chip will cause the entire chip to fail assembly. Low Planarity can be caused by bubbles being trapped in the bump vias, where the bubbles either cause the plated in vias not having trapped bubbles, or prevent bumps from being plated at all. As the number of bumps per chip increases, the chance that one of the bump vias on a chip will catch a bubble increases.
When wafers are bump plated in a face down orientation, the only known way to plate tall bumps and at the same time prevent planarity yield loss is to pattern photoresist which has a low aspect ratio, i.e., shallow bump vias. To get a tall bump when the aspect ratio is low, the bump must be overplated so that it has a mushroom shape. The head of the "mushroom" is formed by plated metallization which spreads laterally along the surface of the photoresist after the plating process has formed a bump as high as the thickness of the photoresist. This overplate, or mushroom head, can lock the photoresist to the wafer, complicating the final removal of the photoresist. Also, the bumps can be placed no closer together than the amount of overplate for two adjacent bumps, limiting the bump density on a chip. For example, if the bump overplate is 1 mil then the bumps must have at least 2 mils separation between them on the wafer.
A further disadvantage of the fixtures disclosed in U.S. Pat. No. 4,137,867 is that any presoak or cleanup treatments needed by the wafers prior to plating must be done before the wafers are mounted in the fixtures, since the fixtures cannot easily be moved, if at all. Presoak or cleanup refers to the removal of oxides and the like from the face of a wafer prior to beginning the plating process itself. If a wafer dries out after cleanup, oxides reform on its surface and the wafer must be recleaned in the cleanup bath. To prevent reoxidation, a wafer must be placed in the plating bath within approximately ten seconds after removal of the wafer from the cleanup bath.